This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-205423, filed Jul. 6, 2000, the entire contents of which are incorporated herein by reference.
This invention relates to a semiconductor integrated circuit and a layout design method thereof and more particularly to a waveform correction circuit used in a logic LSI, for example, for providing countermeasures against clock skew of two-phase clock wires.
Generally, in the logic LSI, the clock propagation delay of a clock wiring used for transmitting a clock signal supplied from a clock signal source to an internal circuit becomes larger as the load capacitance including the wiring capacitance and wiring resistance (which vary in proportion to the length of the wiring) and the terminal capacitance of an internal circuit element becomes larger. Therefore, a clock buffer circuit is inserted at a halfway portion of the wiring. In this case, in the two-phase clock wiring used for transmitting two-phase clock signals supplied from the two-phase clock signal source (clock driver circuit) to the internal circuit, a difference between the delay amounts of the two-phase clock signals becomes important.
FIG. 1 shows one example of a two-phase clock wiring system in the conventional logic LSI and internal circuits connected thereto.
In FIG. 1, reference numeral 10 denotes a two-phase clock wiring which includes a first clock wire 11 and second clock wire 12.
A first latch circuit 15 determines or holds input data supplied thereto via a data signal line in response to the falling edge of a first clock signal xcfx861 from the first clock wire 11.
A second latch circuit 16 fetches data from an output node Q1 of the first latch circuit 15 in response to the rising edge of a second clock signal xcfx860 from the second clock wire 12 and outputs latched data from an output node Q2.
FIG. 2 shows one example of waveforms of the clock signals xcfx861, xcfx860 of the two-phase clock wires 11, 12 shown in FIG. 1 and operation waveforms of the two cascade-connected latch circuits 15, 16. FIG. 3 shows an enlarged portion of the waveforms of the two-phase clock signals xcfx861, xcfx860 in FIG. 2.
As shown in FIGS. 2 and 3, the two-phase clock signals xcfx861, xcfx860 have waveforms each having a period xe2x80x9cLxe2x80x9d (low level) and a period xe2x80x9cHxe2x80x9d (high level) which are set in an approximately complementary relation, a period of the same level (spacing period) exists between the trailing edge of the high level portion of one of the signals and the leading edge of the high level portion of the other signal and a period of the same level (spacing period) also exists between the leading edge of the high level portion of the former signal and the trailing edge of the high level portion of the latter signal. In this example, a spacing period (between a broken line a-b and a broken line c-d) of xe2x80x9cLxe2x80x9d exists between the falling edge of xcfx861 and the rising edge of xcfx860 and a spacing period of xe2x80x9cLxe2x80x9d exists between the falling edge of xcfx860 and the rising edge of xcfx861. Thus, the latch operation and the output operation of the two latch circuits 15, 16 which are cascade-connected as described before are correctly effected.
For example, as shown in FIG. 4, there occurs a possibility that a period which is originally set as the spacing period of xe2x80x9cLxe2x80x9d will become a racing period (between a broken line e-f and a broken line g-h) in which the signals are set at xe2x80x9cHxe2x80x9d due to a difference between the blunted or rounded portion of the waveform of xcfx860 and the blunted or rounded portion of the waveform of xcfx861 in some cases. As the cause of a difference between the blunted portion of the waveform of xcfx860 and the blunted portion of the waveform of xcfx861, it is considered that the load of the first clock wire 11 and the load of the second clock wire 12 are made different by branching the first clock wire 11 on the input side of the first latch circuit 15 as indicated by broken lines in FIG. 1 and connecting the same to a different circuit 15a, for example. Further, the above difference may occur in a portion separated far apart from the clock generating source and connected thereto via a long clock wire in a semiconductor chip.
If the racing period thus occurs, the latch operation and the output operation of the two latch circuits 15, 16 which are cascade-connected as described before are not correctly effected in some cases. For example, if the waveform of xcfx861 is blunted or rounded as indicated by broken lines in FIG. 2, data fetching timing in the first latch circuit 15 is deviated and the second latch circuit 16 will fetch erroneous latched data of the first latch circuit 15 and output erroneous data. The same operation occurs when the blunted or rounded portion of the waveform of xcfx860 becomes different from the rounded portion of the waveform of xcfx861.
That is, in a case wherein the two-phase clock wires 11, 12 are long, the wiring lengths thereof are different from each other (the resistances thereof are different) or the numbers of circuits such as latch circuits respectively supplied with the clock signals xcfx860 and xcfx861 are different (the capacitances thereof are different), then a difference between the loads for the xcfx860 and xcfx861 larger than expected occurs, the balance therebetween cannot be maintained, the timing relation between the falling edge and the rising edge of xcfx860 and xcfx861 is reversed, a spacing period of the two-phase clock signals xcfx860 and xcfx861 cannot be attained in portions of the paths of the two-phase clock wires 11, 12 and a racing period occurs. As a result, a period in which the first latch circuit 15 supplied with xcfx861 as the clock input and the second latch circuit 16 supplied with xcfx860 as the clock input as described before are both turned ON occurs and the latch operation and the output operation of the two cascade-connected latch circuits 15, 16 are not correctly effected.
Therefore, in the prior art, in order to prevent the predictable occurrence of a racing period, two-phase clock signals having a relatively long spacing period are generated from the two-phase clock signal source, but when a computer aided design (CAD) apparatus is used for LSI layout design, attention which is so delicate and adequate as in a case of manual design by a designer is not always given and there occurs a possibility that such a racing period as described above occurs in the circuit portion of a real product in which the spacing period is required.
A semiconductor integrated circuit according to a first aspect of this invention comprises a clock signal source configured to generate two-phase clock signals having spacing periods; a two-phase clock wiring configured to transmit the two-phase clock signals to a plurality of internal circuits constructing the integrated circuit; and a waveform correction circuit having a plurality of MOS transistors of the same conductivity type which are connected between the two-phase clock wiring and a preset potential node and constructed to attain spacing periods of the two-phase clock signals.
A layout design method of a semiconductor integrated circuit according to a second aspect of this invention comprises the steps of arranging a plurality of circuit cells; arranging wires including two-phase clock wires; and distributing and arranging a plurality of MOS transistors for waveform correction connected between the two-phase clock wires and a preset potential node to attain spacing periods of the two-phase clock signals in spaces other than areas in which the plurality of circuit cells of an integrated circuit chip and the wires are arranged.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.